1. Field of the Invention
The present invention relates to a memory device.
2. Description of the Related Art
Recently, a readout system of a ferroelectric memory called a bit line GND sense system has been proposed (for example, refer to patent document 1 and non-patent document 1). In the readout system of this kind, in order to prevent the voltage of a bit line from varying when a voltage is applied to a plate line, electric charges to be read out from a memory cell to the bit line are transferred to a charge accumulation circuit via a charge transfer circuit called a charge transfer formed in a pre-sense amplifier, and the logic value of the data stored in the memory cell is judged in accordance with the amount of electric charges transferred to the charge accumulation circuit. The charge transfer is configured by a p channel MOS transistor. In the p channel MOS transistor, the voltage between gate and source is initially set to the same value as that of a threshold voltage before the plate line is activated. The gate of the p channel MOS transistor is controlled by an inverter amplifier that lowers the output voltage in accordance with a rise in the voltage of the bit line.
[Patent document 1] Japanese Patent Application Laid-open No. 2002-133857
[Non-patent document 1] IEEE Journal of Solid-State Circuits, Vol. 37, No. 5 pp592-597, May 2002
In the bit line GND sense system, the readout operation is performed in such a way that a control circuit causes electric charges to flow by opening the gate of the charge transfer circuit with a slight rise of the bit line and the bit line returns to the ground again.
The memory judges the difference between an increase in potential due to electric charges that come out when data “1” is read (P term) and an increase in potential due to electric charges that come out when data “0” is read (U term) by amplifying it with a sense amplifier. However, miniaturization advances and a cell is reduced in size, not only the amount of polarized electric charges Qsw(P−U) but also the respective amounts of P term and U term become smaller, therefore, the ratio in which electric charges are absorbed in a parasitic capacity in the circuit increases and the peak to which the bit line rises is reduced considerably. Due to this, the control circuit is put into a state in which it does not open the charge transfer circuit sufficiently and there arises a problem of decrease in readout margin.